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Disclosed is a circuit implemented within a DMA Controller to detect illegal tag table entries, and to use the occurrence of an illegal entry to signal the controller that all DMA transfers are complete.
English (United States)
This text was extracted from a PDF file.
This is the abbreviated version, containing approximately
52% of the total text.
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Implementation of Last Tag Indicators Using Illegal Tag Table Entries
Disclosed is a circuit implemented within a DMA Controller to detect illegal
tag table entries, and to use the occurrence of an illegal entry to signal the
controller that all DMA transfers are complete.
The circuit described is used within a serial link adapter. The DMA controller
portion of the adapter controls the flow of data between the serial link and the
system main storage. In order to access information from main storage at the
correct address, a tag table is provided which is loaded by the system, and
contains the addressses of data to be accessed, along with offset and line count
information. The address information is simply the memory page where data will
be accessed. The offset field contains the 6-bit value of the starting location
within a memory page where data will be accessed. The line count field contains
a 6-bit value identifying the number of cache line transfers to be performed at the
page identified by this tag table entry. In this implementation, there exists 16 tag
When the DMA Controller is signalled to begin the transfer process, offset
and line count information is loaded into counters and checked for validity.
Validity is determined by comparing these two values. If, the line count is larger
than the total number of lines available for transfer as defined by the offset, then
the tag is not valid. In addition, if, when the tag is retrieved from the table, a
parity error is detected, the tag is assumed to b...