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Disclosed is a method of transferring electronic data across asynchronous logic boundaries through a RAM.
English (United States)
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Multi-Clocked Synching Data Buffer RAM
Disclosed is a method of transferring electronic data across asynchronous
logic boundaries through a RAM.
This transfer has a main chip controller to assign three asynchronous logic
parititions to the RAM. This method provides asynchronous data transfer using
the smallest amount of logic.
The data paths, address paths, and write clock are multiplexed to match
whichever paritition has control at any given time. Actual switching is done by
the main chip controller.
These are the key design issues:
- Each uniquely clocked control section must maintain its own
address pointer. This pointer needs to be passed to other sections
to indicate how much data is in the RAM.
- The write clock switching must be designed with great care to
prevent RAM timing problems due to skew/delay intro duced by
the write clock multiplexer.
- The buffer must be assigned to the main chip clock during LSSD
and chip self-test. Thus, the other sections will lose some