Browse Prior Art Database

Special Planar Manufacturing Tests in Ros

IP.com Disclosure Number: IPCOM000038160D
Original Publication Date: 1989-Dec-01
Included in the Prior Art Database: 2005-Jan-31

Publishing Venue

IBM

Related People

Authors:
Denison, R Pancoast, S Yee, T [+details]

Abstract

This disclosure describes that concept of eliminating the need for special test fixtures for new planar boards by using an improved Power On Self Test (POST) that logs the error codes, etc. in the nonvolatile storage provided by the Real Time Clock (RTC). When the planar is placed into the stress chamber, only power and memory need be connected to the the planar board. Once power is applied, POST clears the time in the RTC marking the beginning of the test. POST then begins looping on its self tests. When an error is encountered, POST logs the loop count and error code into the RTC.