Browse Prior Art Database

Bi-Level Integrated System Structure

IP.com Disclosure Number: IPCOM000038166D
Original Publication Date: 1989-Dec-01
Included in the Prior Art Database: 2005-Jan-31

Publishing Venue

IBM

Related People

Authors:
Dietsch, HE Nestork, WJ Pricer, WD [+details]

Abstract

Integrated circuit (IC) chips are mounted in a package having thermal expansion equal to that of the chips. An electrical distribution system within the package provides ground and voltage planes plus signal wiring over the ground plane to provide impedance matching. The package has covers which provide environmental protection and good heat transfer. Provision for pressure connecting flex cable is included in the package design. This packaging system structure thus provides opportunity to use any of several chip connecting technologies, including solder reflow, environmental protection with good thermal dissipation, and impedance matched wiring for high speed signal transmission.