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Parity Generator Integrated With Latches

IP.com Disclosure Number: IPCOM000038357D
Original Publication Date: 1987-Jan-01
Included in the Prior Art Database: 2005-Jan-31

Publishing Venue

IBM

Related People

Authors:
Moser, JJ [+details]

Abstract

A method is described for implementing a parity function in conventional level sensitive scan design (LSSD) shift register latch (SRL) strings allowing simple diagnosis of single-bit faults. The method consists of adding an exclusive OR (XOR) gate to an LSSD SRL and of a technique of interconnecting the added XOR gates to comprise a parity generator for all latches on a chip. An LSSD SRL is a master-slave latch which is synchronized with two phase clocks, hereinafter referred to as clocks C and B, plus an auxiliary port provided to a master latch which is synchronized with a third clock, referred to as the A clock. The clocks are omitted from the figures. The data into the auxiliary port is either connected to a primary input or else the output of another slave latch.