Decoded Bitline Structures for High Performance Sensing in Semicon-Ductor Dynamic Memory
Original Publication Date: 1987-Jan-01
Included in the Prior Art Database: 2005-Jan-31
A decoded bitline structure is described which gives smaller bitline capacitance before sensing, faster signal transfer from bitlines to I/O bus, and does not need extra depletion devices and extra PMOS cross- coupled latches. As the density of DRAM (dynamic random-access memory) chips increases, the number of memory cells (bits) associated with the first- stage sense amplifier also has increased. The reason for this increase is that as the memory cell size becomes smaller, the peripheral-circuit overhead should be reduced by decreasing the number of sense amplifiers and column decoders. However, as the number of bits per bitline increases, either the differential signal for sensing becomes smaller or the cell capacitance has to be increased.