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Simplified Static Column Decoder for CMOS Memory Bit Switches Disclosure Number: IPCOM000038385D
Original Publication Date: 1987-Jan-01
Included in the Prior Art Database: 2005-Jan-31

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Related People

Redman, TM Webb, C [+details]


This article relates to a simplified column decoder used to control bit switches in complementary metal-oxide-semiconductor (CMOS) memories by reducing circuit count, area and predecoder loading. A higher density memory is possible by reducing device counts, resulting in less chip area and power required for bit switch decoding. This is done by modifying the CMOS NAND static column decoder circuit. Shown in Fig. 1 is a basic CMOS NAND column decoder circuit design used in many current memory designs. Predecoder lines (Zx) and line A8C and A8C not drive decoder transistors 0-4 and 0'-4'. P type pull-up transistors (0'-4') are used to minimize active CMOS NAND power requirements, but increase the number of decoder devices and double the load on predecoder drive circuits.