Split Emitter MTS Memory Cell
Original Publication Date: 1987-Jan-01
Included in the Prior Art Database: 2005-Jan-31
An array cell has been developed for semiconductor devices which is smaller and faster than conventional cells. It is a merged transistor switch (MTS) cell with cross-coupled PNP's, split PNP emitters, and NPN loads. In conventional MTL cells a discharge process is required for access [*]. This leads to delays and circuit complexities. The complementary transistor switch (CTS) cell is fast in read, but the cell size is relatively large. The write, meanwhile, is slow unless the NPN Tx b is artificially degraded. The proposed MTS cell is free from the foregoing problems, having combined features of the MTL and CTS cells. As compared to conventional CTS cells, no separate I/O devices are required in the configuration (Fig. 1).