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Dynamic Memory Refresh Control for Long but Finite Computer Operations

IP.com Disclosure Number: IPCOM000038423D
Original Publication Date: 1987-Jan-01
Included in the Prior Art Database: 2005-Jan-31

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Sotolongo, H [+details]


A technique is described whereby the dynamic memory refresh operation within a computer storage control unit is controlled by counter circuitry to provide an increase in the overall processing speed of the computer. Refresh operations are not possible during operations in which storage access resources are at capacity limits. The subject technique retains the number of outstanding memory refresh requests in a counter, so that the refreshes will occur back to back when the long memory operation is complete. In the prior art, dynamic memory refresh operations required that the portion of memory being refreshed be termed as busy and therefore that portion of memory was inaccessible for use until the refresh was complete.