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Clustering Drain Line for Harper Array

IP.com Disclosure Number: IPCOM000038460D
Original Publication Date: 1987-Jan-01
Included in the Prior Art Database: 2005-Jan-31

Publishing Venue

IBM

Related People

Authors:
Eardley, DB Michail, MS [+details]

Abstract

A layout and electrical circuit design technique have been developed for minimizing the variation of differential voltages across the cell between the word line and drain line in semiconductor devices. This makes it possible to eliminate the emitter resistor (RE), thereby saving space on the chip. Because of the word line and drain line resistance the voltage across an array of cells will not be equal. This causes the cell currents to vary from one cell to the other, which may affect the stability of the cell. In the design of the Harper cell an RE is usually used to avoid this current hogging. While the RE is effective, it has the disadvantage of occupying space on the chip which may be better utilized.