Browse Prior Art Database

Method for Interlacing Processor Memory Accesses to a Display Buffer With Screen Refresh Display Buffer Accesses

IP.com Disclosure Number: IPCOM000038514D
Original Publication Date: 1987-Jan-01
Included in the Prior Art Database: 2005-Jan-31

Publishing Venue

IBM

Related People

Authors:
Arismendi, A [+details]

Abstract

In the prior art, application programs need to monitor a status register and wait for horizontal or vertical sync dead time to update or read the display buffer. In the new method, interlacing processor accesses with the refresh accesses eliminate the memory contention which causes display static of flicker. Display adapters for cathode ray tube (CRT) monitors and television sets recommend that any updating or reading of the display buffer be done during horizontal or vertical sync dead time. This is to avoid the hashing or static that will occur due to display memory contention. Others require that the video to the display be turned off during the updates or reads. This method avoids the need to wait for horizontal or vertical syncs, but the result is a flicker of the contents on the screen.