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Fault-Detecting Adder

IP.com Disclosure Number: IPCOM000038532D
Original Publication Date: 1987-Jan-01
Included in the Prior Art Database: 2005-Jan-31

Publishing Venue

IBM

Related People

Authors:
Woodward, SS [+details]

Abstract

This concept relates to a class of binary adders consisting of a first module followed by a series of identical modules. Each module accepts one or more bits of each of the operands and delivers the corresponding number of sum bits. The last module also delivers the carry, the sum parity, and an error-indication signal. The design is such that all single stuck-at faults, which deliver a wrong output, will raise the (Image Omitted) error indication. The characteristic, unique feature of these adders is a design which adheres to a certain set of rules given below. Furthermore, there is a simple set of diagnostic inputs which can be used to detect all single stuck-at faults in the adder provided they are not masked by internal logical redundancies. The adder must be of a modular structure, as depicted in Figs. 1 and 2.