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HIGH Performance Word Decoder for Bipolar Ram Disclosure Number: IPCOM000038534D
Original Publication Date: 1987-Jan-01
Included in the Prior Art Database: 2005-Jan-31

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Chan, YH [+details]


This article describes a word line decoder/driver circuit employing the intrinsic device capacitance (diffusion capacitance) of an inverse transistor for speed enhancement. Fig. 1 shows a word line decoder/driver circuit. It includes a current switch decoder input stage and double-ended push-pull driver outputs to drive two half arrays. One limitation of this circuit is its deselection speed, which is determined by the fall time of node 1 and the active pull-up rate of the upper word line (WL). Due to the double- ended driving, node 1 is heavily loaded and its switching speed is limited by the Current Switch current. The disclosed circuit shown in Fig. 2 uses a novel capacitor speed enhancement technique to improve the time of node 1.