QUARTER VDD SENSING SCHEME IN CMOS DRAM
Original Publication Date: 1987-Jan-01
Included in the Prior Art Database: 2005-Jan-31
This article describes a new sensing scheme with a quarter VDD precharge method whose access time can be much faster than half VDD sensing in a high performance CMOS DRAM (complementary metal-oxide-semiconductor dynamic random-access memory) design. The quarter VDD sensing (QVS) is so-called because bitlines are precharged to VDD-VTN, in which VTN is the threshold voltage of an NMOS transistor and is close to a quarter of VDD. This new sensing technique will be useful in designing even faster CMOS DRAM circuits. Fig. 1 shows the circuit diagram for scheme, where NMOS transistors Q1 and Q2 precharge the bitlines (BL and BLN) to VDD-VTN when PEQ is high at VDD for a p-channel array. Q3 further equalizes the bitline potential. It should be noted that removal of Q1 and Q2 would result in conventional half VDD sensing (HVS). Fig.