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Hierarchical Placement and Wiring With Relaxation for VLSI Gate Arrays

IP.com Disclosure Number: IPCOM000038589D
Original Publication Date: 1987-Feb-01
Included in the Prior Art Database: 2005-Jan-31

Publishing Venue

IBM

Related People

Authors:
Burstein, M Kurtzberg, JM Youssef, MN [+details]

Abstract

A technique for global routing improvement within a hierarchical placement and wiring (HPW) method for the layout of VLSI gate arrays introduced in [1] is described herein. The method was recently modified [2] to resolve the critical nets problem. The (HPW) placement routine is based on successive partitioning of the network logic. The partitioning algorithm is concerned with moving one component (circuit) at a time across a partitioning line. A component is allowed to cross a partitioning line only once [3,4]. This restriction, while necessary to avoid thrashing (movement of circuits back and forth), may influence the quality of the placement, since this mode of operation is obviously dependent on the order of selection of these components.