Fast Serializer for Graphics Display
Original Publication Date: 1987-Feb-01
Included in the Prior Art Database: 2005-Jan-31
In a color graphics display, 8 pels (picture elements) are read out from an n plane store in parallel. These 8 pels require conversion into a serial stream of n-bit-wide data. The serializer is implemented in Level Sensitive Scan Design (LSSD) logic using 5n latches. In order to fit LSSD design rules, the pel rate clock is divided by two to generate two alternate clocks for driving the latches. To serialize data coming from n planes of memory into a stream of n-bit-wide data the serializer clock is too fast to be an LSSD B/C clock without division. As shown in Fig. 1 the pel-rate clock is divided by 2 and used to generate fast A/C and fast B on alternate cycles. These fast clocks are used to drive dual-ported L1-L2 latches to serialize to pel pairs. The pel pairs are then serialized to pels using L1-L2* latches.