Browse Prior Art Database

Automated Chip Array Testing

IP.com Disclosure Number: IPCOM000038604D
Original Publication Date: 1987-Feb-01
Included in the Prior Art Database: 2005-Jan-31

Publishing Venue

IBM

Related People

Authors:
Harrison, BR Norris, PW Wood, RT [+details]

Abstract

In semiconductor gate arrays, designs complying with scan design rules, such as Level Sensitive Scan Design (LSSD), can be tested with automatically generated test patterns whereas non-LSSD designs require manually generated test patterns. When a mixture of LSSD and non-LSSD is required, non-LSSD portions may be isolated during automatic generation of test patterns. The technique reduces the number of manually generated test patterns required. In many gate array designs, cell count is often a significant constraint. Such designs may contain arrays of registers (such as register files, FIFOs, etc) comprising many latches all controlled by common, combinatorial logic, consuming large numbers of the cells available.