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Contact Via Definition Where Quartz Insulation of Metal Lines Is Required

IP.com Disclosure Number: IPCOM000038624D
Original Publication Date: 1987-Feb-01
Included in the Prior Art Database: 2005-Jan-31

Publishing Venue

IBM

Related People

Authors:
Chaloux, PN Houghton, TF [+details]

Abstract

Disclosed is a process which permits selective etching of masterslice contacts and insulator in quartz-based semiconductor devices. The process does not use lift-off to define contact stud patterns, thereby avoiding any lift-off constraints. (Image Omitted) When quartz is sputtered onto a silicon masterslice substrate having metallized lines, the surface topography is not planar. Subsequent reactive ion etch (RIE) of the vias becomes difficult to control and has a tendency to damage the contacts on the substrate. While many semiconductor devices require quartz insulation of the metal lines, there are inherent limitations imposed because the masterslice contacts are chemically similar to the insulating materials.