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Manufacturing Process and Test Method for Masterslices With Non-Personalized First Metal Masks

IP.com Disclosure Number: IPCOM000038629D
Original Publication Date: 1987-Feb-01
Included in the Prior Art Database: 2005-Jan-31

Publishing Venue

IBM

Related People

Authors:
Pollmann, K Schettler, H Wagner, O Zuehlke, R [+details]

Abstract

For reducing the manufacturing time of integrated semiconductor circuits, it is proposed that the mask for the first metallization plane not be personalized. For this purpose, the following approach is used. 1) The transistors are wired to the logic basic function, say, a 2 W NAND circuit. Output 0 is wired to input I of the next basic function. 2) The wiring channels of the first metallization plane are filled with long lines 1 (Fig. 2). In edge areas 2 (Fig. 1), they are connected in the form of a meander. Edge areas 2 comprise underpasses 3 in the silicon material which permit all lines to be tested for interruptions and adjacent lines to be tested for shorts.