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Improved Layout for Differential Cascode Emitter Coupled Logic Disclosure Number: IPCOM000038636D
Original Publication Date: 1987-Feb-01
Included in the Prior Art Database: 2005-Jan-31

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Chen, SY Homan, ME Machol, GK [+details]


To achieve high speed for field-manipulation operations, current microprocessors employ high speed arithmetic logic units having circular shift and masking capabilities. Such architecture provides very efficient systems code, and device controller and emulator microcode. A differential cascode mask and merge unit in combination with a rotate array arranged in semi-bit slice configuration is described. Instead of generating the mask directly, the mask is generated by the combination of a right mask generator and a left mask generator. The two masks are combined with a surround bit, rotated word and merge field to form the merged word.