Arrangement to Speed-Up Parallel-Processor Operation
Original Publication Date: 1987-Feb-01
Included in the Prior Art Database: 2005-Jan-31
A concept is described herein which will allow the execution of parallel programs containing serial sections to be notably speeded up, so as to improve the performance of Parallel Processing Systems (PPSs) well beyond that obtainable by conventional parallel-processing techniques. The concept is realized by a hardware arrangement which is provided as a basis to facilitate compilers to automatically generate object-codes that will allow the Processing Elements (PEs) in a PPS to operate in the designated way. The principal concept is the provision of a hardware arrangement to enable the PEs which are idling during the execution of a serial section to start performing work as early as possible for the coming parallel section, thus utilizing the would-be-idle time and shortening the overall processing time.