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Browse Prior Art Database

CECL With Multiple Current Paths

IP.com Disclosure Number: IPCOM000038647D
Original Publication Date: 1987-Feb-01
Included in the Prior Art Database: 2005-Jan-31

Publishing Venue

IBM

Related People

Authors:
Wong, RC [+details]

Abstract

The CECL (cascode emitter coupled logic) network described in this article can be used to increase the density of more complicated logic functions, in gate arrays or custom designs. In the conventional CECL gate shown in Fig. 1, one current path always exists in the logic tree, which reaches one of the two logic tree tops. Two CECL trees are thus needed in the conventional full (Image Omitted) adder in CECL trees of three cascode levels, as illustrated by Fig. 2. For higher density, however, the CECL tree can be so designed that one or more current paths may reach one of the multiple logic tree tops. A logic tree design is here disclosed in which one or more current paths may reach one or more of the logic tree tops.