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Resistive Load for SRAM Cell

IP.com Disclosure Number: IPCOM000038671D
Original Publication Date: 1987-Feb-01
Included in the Prior Art Database: 2005-Jan-31

Publishing Venue

IBM

Related People

Authors:
Hwang, W Wang, LK [+details]

Abstract

This article relates generally to integrated circuit structure and, more particularly, to the fabrication of resistive loads for static random-access memory (SRAM) cells. When load resistors for SRAM cells are constructed in transistor drain junctions, parasitic channels are avoided, resistance can be easily changed and controlled by implantation dosage or species, and only a single set of masks is required. This arrangement uses conventional fabrication techniques and improves density, yield and performance. (Image Omitted) A source/drain junction is formed in the conventional manner, as illustrated in Fig. 1, in which p- layer 1 is expitaxially grown on psubstrate 2 and the active area is defined by recessed field oxide 3.