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CMOS Isolation by Use of a Floating, Self-Aligned N+ Guard Ring Around the N-Well

IP.com Disclosure Number: IPCOM000038672D
Original Publication Date: 1987-Feb-01
Included in the Prior Art Database: 2005-Jan-31

Publishing Venue

IBM

Related People

Authors:
Dally, AJ Ogura, S Riseman, J Rovedo, N [+details]

Abstract

A simplified method has been proposed to prevent latch-up in complementary metal-oxide-semiconductors (CMOS) which integrates a guard ring into the CMOS isolation process of a semi-ROX (recessed oxide) structure. The methodology involves the superimposing of an N+ guard ring around the N-well of the P-channel device. A lift-off embodiment of the N-well mask is used which utilizes a multi-level resist 1 (Fig. 1) with the bottom layer being polyimide. After pad oxidation 4 and Si3N4 deposition 3, the N-well 2 can be implanted. Following the implant, Al 6 is deposited over the structure (Fig. 2). The Al will be thinner and etch faster over the vertical (Image Omitted) edges of the resist mask, and a dip-etch will etch back the Al to the configuration shown in 5, which results in a gap 7 created by the etch- back.