Browse Prior Art Database

Gate Structure

IP.com Disclosure Number: IPCOM000038676D
Original Publication Date: 1987-Feb-01
Included in the Prior Art Database: 2005-Jan-31

Publishing Venue

IBM

Related People

Authors:
Davari, BB Ting, CY [+details]

Abstract

This article relates generally to integrated circuit construction and, more particularly, to transistor gate structure. In submicron CMOS devices, layers of titanium silicide and polysilicon on tungsten silicide gates reduce the gate resistance and the stress on gate oxide. In Fig. 1, silicon substrate 1 has source/drain junction 2 defined by recessed oxide regions 3 and oxide layer 4. Successive layers of tungsten silicide 5, polysilicon 6 and nitride 7 are deposited. Gate 8 is patterned level in Fig. 2, and the source/drain area reoxidized, if necessary. The source/drain is implanted, and nitride layer 7 on the gate polysilicon is etched. Nitride is again deposited and etched to form sidewalls 9, and the source/drain and polysilicon surfaces are cleared by wet etching.