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Raised Source/Drain Structure

IP.com Disclosure Number: IPCOM000038681D
Original Publication Date: 1987-Feb-01
Included in the Prior Art Database: 2005-Jan-31

Publishing Venue

IBM

Related People

Authors:
Davari, B Ning, TH Taur, Y [+details]

Abstract

This article relates generally to CMOS integrated circuit devices and, more particularly, to transistor source/drain junction construction. Shallow source/drain junctions for submicron CMOS technology can be fabricated with lower sheet resistance, lower leakage current and improved reliability by forming a raised conductive shunt film over the source and drain. The construction steps for an n-channel device are described below: In Fig. 1, the source/drain area of substrate 1 is defined by shallow trench isolation oxide 2. Gate oxide layer 3 is grown, and a channel dopant added, if necessary. Gate material 4, such as tungsten, is deposited, and an insulating nitride layer 5 is added over the junction area.