Oscillator Switching Circuit
Original Publication Date: 1987-Feb-01
Included in the Prior Art Database: 2005-Feb-01
In a display system where screen size is selectable, changing screen size requires changing oscillator frequency controlling clocks for Level Sensitive Scan Design (LSSD) logic. This change can cause glitch problems which are avoided by using an asynchronous pulse from the controlling processor during the frequency change. As shown in Figs. 1 and 2, a clock splitter runs from one of two oscillators OLD OSC and NEW OSC, and generates non-overlapping LSSD clocks FASTC and FASTB. When modes are changed, i.e., oscillator frequencies switched, spurious clock pulses can be obtained (the worst two cases being shown in Figs. 1 and 2). If a mode register controls this switching and it is clocked by FASTC and FASTB (i.e.