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Method for Addressing a Two-Dimensional Memory With Address Incrementing Random-Access Memories Disclosure Number: IPCOM000038744D
Original Publication Date: 1987-Feb-01
Included in the Prior Art Database: 2005-Feb-01

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Burroughs, SH Evans, EK Muhich, JS [+details]


A method is described which allows a significant reduction in the complexity of the Dynamic Random-Access Memory (DRAM) addressing circuitry. A method for accessing a two-dimensional memory array in either the horizontal or vertical direction without regard to byte or word boundaries is ******** in the prior art. In that arrangement, memory modules are arranged in the array on a diagonal so that all modules are accessed, each cycle independent of direction of access. An implementation of this addressing method with conventional DRAMs is shown in Fig. 1. In this example, 16 64Kx1 DRAMs are used to create a 1024 x 1024-bit map. A 10-bit X address and a 10-bit Y address are processed by the addressing circuitry to create 16 8-bit row/column addresses.