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XOR and NXOR Performance Improvement Disclosure Number: IPCOM000038746D
Original Publication Date: 1987-Feb-01
Included in the Prior Art Database: 2005-Feb-01

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Blachere, JM Le Garrec, JC [+details]


A possible way to implement an XOR (characterized by a low cell count), as shown in Fig. 1, presents two drawbacks: The delay to an output signal rising can be very high. The load capacitance will be charged through device 1 (or 2) and up to three P channel devices in serial corresponding to the previous stage (in this case a three-way NOR). There is one case where an output signal falling is realized with the load capacitance discharging through device 1 (or 2). The device has its gate connected to "0", thus VGS decreases more and more. The end of the transition is characterized by a high impedance. The up-down transition is not complete, and this reduced swing voltage yields a small delay penalty on the next stage (10% typical).