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Self-Aligned Contoured Electron Barrier for Soft Error Reduction

IP.com Disclosure Number: IPCOM000038751D
Original Publication Date: 1987-Mar-01
Included in the Prior Art Database: 2005-Feb-01

Publishing Venue

IBM

Related People

Authors:
Adler, E Bakeman, PE [+details]

Abstract

This article describes the formation of energy barriers by using deep buried ion implants (DBII) to avoid degradation of circuits and to reduce the soft error rate (SER). The uniqueness of this invention is the use of the polysilicon stack of the storage plate and the first polysilicon photoresist layer as a self-aligned method of profiling the DBII. Hence, no extra mask step is required to implement the invention, and no alignment tolerance noise in the detected signal results. The process to produce the structure consists of implanting (11) the wafer 12 after the first layer of polysilicon 13 is etched, with the photoresist 14 remaining in place.