Active Bus on a Wiring Wafer
Original Publication Date: 1987-Mar-01
Included in the Prior Art Database: 2005-Feb-01
This article describes the concept of a central active bus for interconnecting VLSI chips on a common semiconductor substrate (wafer) in which, in addition to passive wiring, active elements are integrated. The VLSI chips have a high packaging density, whereas the wiring wafer may have a low packaging density but a high yield (say, 1 m technology for the VLSI chips and 5 m technology for the wiring wafer). Known IC production methods, as contrasted to conventional ceramic substrate-based technologies, permit accommodating a large number of interconnections for an equally large number of I/O pins of the VLSI chips on the wafer, which in turn permits using highly effective bus concepts. The bus arbitration logic may be centrally integrated in the wiring wafer.