Browse Prior Art Database

Selectable Up/Down Counter

IP.com Disclosure Number: IPCOM000038794D
Original Publication Date: 1987-Mar-01
Included in the Prior Art Database: 2005-Feb-01

Publishing Venue

IBM

Related People

Authors:
Potter, DW [+details]

Abstract

A binary synchronous up/down counter is described which has a select feature providing capability to do single cycle counts of +1, 2, 3, or 4. _ Fig. 1 shows inputs In (increment) and De (decrement) to counter circuit 2, one of which is activated on each cycle. Inputs x2, x3, and x4, of which one or none is activated each cycle to counter circuit 2, provide instruction for number of steps to be taken (2, 3, or 4). No input on any of the inputs x2, x3, and x4 results in a step by one increment or decrement instruction. Clock CB input to counter circuit 2 triggers shift register latch (SRL) circuits internal to counter circuit 2 by connection to input port C1 of an SRL, one of which is shown in Fig. 2. SRLs used in counter circuit 2 are dual port units. D1 and C1 ports are used for counting functions.