Browse Prior Art Database

Trench Mosfets (3-D Structure)

IP.com Disclosure Number: IPCOM000038797D
Original Publication Date: 1987-Mar-01
Included in the Prior Art Database: 2005-Feb-01

Publishing Venue

IBM

Related People

Authors:
Nijhuis, R Pelella, AR [+details]

Abstract

Conventional field-effect transistor (FET) structures employing horizontal channels do not make very efficient use of available wafer surface area. This may be overcome with the design described in this article in which polysilicon-filled trenches allow formation of FET channels on all sides of the trench. The oxide wall can then be used as (Image Omitted) an FET gate insulator and the trench conductor as a gate electrode, allowing MOSFETs to be constructed with a relatively large width dimension at small cost of wafer area. With the use of a double-trench technology, a vertical MOS transistor can be constructed, as illustrated in Figs. 1 and 2. A trench is first dug into the substrate (p-type) and an oxide lining fabricated between the substrate and the trench cavity.