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Delay Margin Testing Circuit for CMOS Circuitry

IP.com Disclosure Number: IPCOM000038804D
Original Publication Date: 1987-Mar-01
Included in the Prior Art Database: 2005-Feb-01

Publishing Venue

IBM

Related People

Authors:
Gray, KS Kosson, JS [+details]

Abstract

An automated high volume delay margin testing means for critical delay paths in CMOS designs is shown utilizing DC control voltage techniques. Currently a double-inverter circuit configuration, shown in Fig. 1, is used to isolate manually directed orbital probes when making critical delay path measurements on CMOS designs. If automatic testing is required, a probe card connection at node A is needed, but this introduces an unacceptable capacitive load which distorts test results. To increase or decrease delays without changing the rise and fall characteristics of the output pulse, node A is overridden with an AC pulse. This precludes doing margin testing on an automated high volume tester. By using a basic CMOS inverter, shown in Fig. 2, in series with a p-channel device (Fig. 3) or a n-channel device (Fig.