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Simultaneous Definition and Implant of N-Well and P-Channel Source/ Drain

IP.com Disclosure Number: IPCOM000038817D
Original Publication Date: 1987-Mar-01
Included in the Prior Art Database: 2005-Feb-01

Publishing Venue

IBM

Related People

Authors:
El-Kareh, B Gravenites, GG Puttlitz, AF [+details]

Abstract

This article relates to a simultaneous self-aligned n-well and p- channel source/drain implant technique which eliminates a mask step when fabricating CMOS memories. In conventional CMOS processes for fabricating static and dynamic random-access memories, n-wells are defined and ion implanted (I/I) using an extra masking step prior to the p-channel source/drain (S/D) definition. The disadvantages of this process are: 1) Need for a masking step. 2) Alignment tolerances imposed on the p-channel pockets to n- well. 3) Spacing between n-channel pockets and n-well must be adequate to insure against punch through. 4) Phosphorus pile-up during oxidation cycles. The figure shows a semiconductor structure with a photoresist mask 11 on top of an oxide insulator 12.