Browse Prior Art Database

Modification of Interlevel Via Design to Lower Line Resistivity

IP.com Disclosure Number: IPCOM000038822D
Original Publication Date: 1987-Mar-01
Included in the Prior Art Database: 2005-Feb-01

Publishing Venue

IBM

Related People

Authors:
Cronin, JE Kaanta, CW [+details]

Abstract

A technique is described for lowering the resistance of metal lines used to connect semiconductor circuits without changing the material used to fabricate the metal lines. Fig. 1 shows the conventional method used for wiring circuits on a chip when two levels of metal are used. Metal level two (M2) is used to connect metal level one (M1) points A and C by bridging point B. By replacing metal-filled round via studs with metal-filled troughs, shown in Fig. 2, a lower resistance interconnect method can be achieved. The trough has a minimum via size in one dimension (Y) and is as long (X) as needed to connect A' and C' but may not intersect a bridge zone 10 with underpass line B'. The trough length X may not be less than 2X long when gap-fill techniques which grow from the surface up are used to fill a trench.