New Fast Page Mode Design in CMOS Dynamic Ram
Original Publication Date: 1987-Mar-01
Included in the Prior Art Database: 2005-Feb-01
This article describes a new fast page mode design for CMOS DRAM (dynamic random-access memory), which has much faster column access time and shorter cycle time in contrast to conventional page mode design. Fig. 1 shows the timing diagrams of conventional page mode and the new fast page mode. In conventional page mode design, CAS low activates the address buffer and then decoder which selects the column switch to allow data transfer from bit-lines to an input/output sense amplifier. When CAS is high, the column circuit is reset (precharged) and prepared ready for the next active cycle. The column cycle time includes the time for address buffer, column decoder, I/O sense amplifier, data output buffer, data valid, and column precharge.