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Recovery Mechanisms for Fetch&op Instruction Execution Errors

IP.com Disclosure Number: IPCOM000038891D
Original Publication Date: 1987-Mar-01
Included in the Prior Art Database: 2005-Feb-01

Publishing Venue

IBM

Related People

Authors:
Malek, M Rathi, DB [+details]

Abstract

The Fetch&Add (x, A) instruction was introduced by the NYU Ultracomputer [3]. The RP3 project [1] generalized this instruction to Fetch&Operation (x, A), called Fetch&OP herein. This Fetch&OP instruction first reads the contents of location "A" of a memory. It then applies the necessary operation "OP" on this data and the instruction's operand "x". It then stores (if needed) the intermediate or final result of this operation and returns the result. This instruction executes in an indivisible manner. This instruction is executed at the memory and is supported by the combining network [2] of the RP3 computer. The main advantages gained by shared memory parallel computers (e.g., RP3) by supporting this instruction are: 1.