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Ternary Semiconductor Superconducting Device

IP.com Disclosure Number: IPCOM000038906D
Original Publication Date: 1987-Mar-01
Included in the Prior Art Database: 2005-Feb-01

Publishing Venue

IBM

Related People

Authors:
Brady, MJ Davidson, A Frank, DJ Kleinsasser, A Woodall, JM [+details]

Abstract

The use of a ternary alloy of InGaAs for a collector isolator and the insulation of the surface thereof with a p-n junction provides the ability to provide control of the barrier height at the base interface while providing general insulation. The device is shown in Fig. 1, with an energy diagram in Fig. 2 illustrating the use of a p-type layer to provide insulation between metal and n-InGaAs, and Fig. 3 is an energy diagram illustrating the position of the conduction band with 20% In concentration at the base, which In concentration sets the conduction band position. The semiconductor would be grown in layers in an epitaxial process, as shown in Fig. 1. The substrate would be a GaAs wafer, which is known to be suitable for epitaxial growth of InGaAs. The lowest layer grown on the GaAs would be n+ InGaAs, of the order of 0.