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Selectable BUS Byte Order Circuit

IP.com Disclosure Number: IPCOM000038923D
Original Publication Date: 1987-Mar-01
Included in the Prior Art Database: 2005-Feb-01

Publishing Venue

IBM

Related People

Authors:
St. Clair, JC [+details]

Abstract

The figure illustrates a circuit that allows a feature card to be attached to two styles of system buses: those that define data bits 0-7 as the most significant bits, and those that define data bits 8-15 as the most significant bits. Some systems define data bits 0-7 to be the Least Significant Byte (LSB) while bits 8-15 form the Most Significant Byte (MSB). Other systems define bits 0-7 to be the MSB and bits 8-15 to be the LSB. When attaching a feature card to either of these two styles of systems, the circuit described below allows the byte ordering to be correct for both system styles.