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Partitioned Wordline for High Performance Memory

IP.com Disclosure Number: IPCOM000038949D
Original Publication Date: 1987-Mar-01
Included in the Prior Art Database: 2005-Feb-01

Publishing Venue

IBM

Related People

Authors:
Chin, D Lu, N [+details]

Abstract

In a high density static random-access memory (SRAM) or dynamic random- access memory (DRAM), many access transistors, typically 1K for a 1 Mb DRAM, are connected to a wordline in parallel. Capacitance of all the gates is a heavy load to the wordline driver, which can cause a dominant delay in memory access time. In order to reduce RC delay of the wordline, the polysilicon gate is silicided or a second metal layer is used to patch the long wordline. These techniques are aiming at reducing the wordline resistance. However, there are technology and material limits in lowering the resistance (currently a few ohms per square for silicide). As the line width becomes narrower, the number of squares on a metal or polysilicon wire becomes larger. This will increase the resistance and thus the delay time.