Clock-Free Latched Sense Amplifier for Bipolar RAM
Original Publication Date: 1987-Apr-01
Included in the Prior Art Database: 2005-Feb-01
The present disclosure describes a sense amplifier which includes a latch for the data out in order to take place in a clocked bipolar random-access memory (RAM) because it is directly set/reset by means of the bit line current. In a typical application, the circuit may be used in a 36K RAM, physically organized as a 144 x 256-cell matrix, and logically as a 2K x 18. It is a clocked RAM; this means that in stand-by mode, each cell is deselected and 18 pairs of bit line current (IBL) sources are ON among 144. These 18 pairs of IBL sources which are ON correspond to the previous bit address which has been stored in a special "address latch".