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Optimal Sequential Testing Scheme for VLSI Circuits

IP.com Disclosure Number: IPCOM000038975D
Original Publication Date: 1987-Apr-01
Included in the Prior Art Database: 2005-Feb-01

Publishing Venue

IBM

Related People

Authors:
Lee, YH Yu, PS [+details]

Abstract

This invention provides an efficient testing scheme that applies the optimal testing period to test VLSI circuits and simultaneously estimates production yield. As the density of VLSI circuits increases, the testing pattern applied to the VLSI circuits can no longer test for all possible defects. Therefore, minimum testing needs must be determined. In general, there are two kinds of costs associated with the testing process: the cost of testing itself and the cost of passing as good an imperfect circuit. An optimal testing strategy should trade off both costs and determine an adequate test length (in terms of testing period or number of test patterns).