Address LATCH With Intermediate Reference
Original Publication Date: 1987-Apr-01
Included in the Prior Art Database: 2005-Feb-01
The present disclosure describes a latched receiver with improved AC performances based on the use of a third transistor connected to an intermediate reference. (Image Omitted) The latter leads to a faster data acquisition, and the latch current source does not need to be switched any more. Principle (Fig. 1) When an address is stored in the address latch (ADD LATCH), CLK is pulled up and CLK is pulled down. Because the latch content is isolated from the data bus, it can be used to provide the reset data. Then, data has to be present on the bus at least during the clock pulse and the address signal skew is avoided. A special intermediate reference for the address latch improves the minimum clock pulse requirement. Description of the invention (Fig. 2) Both the receiver and the latch are ECL (emitter coupled logic) circuits.