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Differential Receiver With Hysteresis

IP.com Disclosure Number: IPCOM000039000D
Original Publication Date: 1987-Apr-01
Included in the Prior Art Database: 2005-Feb-01

Publishing Venue

IBM

Related People

Authors:
Ippolito, PM [+details]

Abstract

A differential off-chip signal receiver circuit with built-in hysteresis is disclosed. The hysteresis effect is beneficial in improving both the AC and DC noise tolerance of the receiver circuit. Transistors T1, T2, T3, and T4 provide an emitter coupled differential receiver circuit. The hysteresis effect is achieved through the combined action of TXOUT and TXHYS, which modulate the effective reference voltage seen by the base of T2. When the input signal is high, TXOUT will turn on TXHYS as determined by the ratio of R1 and R2. TXHYS on lowers the voltage at the base of T2. This lowers the switching threshold for the down-going signal transition and improves the up-level noise margin of the receiver. When the input signal is low, TXHYS will be off. The voltage then seen by the base of T2 is VR.