Two-Party Bus Arbitration for Floating-Point Operation
Original Publication Date: 1987-Apr-01
Included in the Prior Art Database: 2005-Feb-01
A technique is described whereby a tightly coupled bus arbitration logic concept is used in high utilization floating-point computer operation, so as to provide fast transferring of operands to multiple and divide sub-units of a two-chip floating-point unit (FPU). The arbitration scheme is applicable to two-party bus floating- point operations, where one party requires 100% usage and control of the bus and will release the bus to requesters on all occasions, yet can force the requester to keep the bus when the owner requires the result for a longer period of time. The arbitration bus is used between the two chips (upper and lower) of the FPU. It is a data bus used for transferring operands to the multiple and divide sub-units on the lower FPU and for transferring the results back to the upper FPU.