Browse Prior Art Database

Bit Address Decoder Coupled With Bit Line Leakage Absorber

IP.com Disclosure Number: IPCOM000039028D
Original Publication Date: 1987-Apr-01
Included in the Prior Art Database: 2005-Feb-01

Publishing Venue

IBM

Related People

Authors:
Omet, D [+details]

Abstract

The present disclosure describes a bipolar circuit which realizes a bit address decoder for a static RAM (random-access memory). It can be seen as a composition of three functions, which are explained below: a bit address TCG (True Complement Generator), a bit line (BL) pull-up circuit, and a cell leakage absorber (Fig. 1). 1.Bit address TCG The output of this circuit behaves as an active pull-down, in order to prevent multiple-bit selection when the add is changed. The output swing has been minimized to ensure functionality and fast bit selection. These two levels are: - VBE(T3) [1+R1/R2] --> BL sources ON - VF (S1) --> OFF 2. Bit line pull-up circuit For a selected column IBL is ON, then pull-up current source IPU is also ON, and the base voltage of the two transistors TPU is equal to (3 VBE - RPU . IPU).