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Gallium-Doped Titanium Silicide for Low Contact Resistivity

IP.com Disclosure Number: IPCOM000039102D
Original Publication Date: 1987-Apr-01
Included in the Prior Art Database: 2005-Feb-01

Publishing Venue

IBM

Related People

Authors:
d'Heurle, FM Harrison, HB Iyer, SS Michel, AE Sai-Halasz, GA [+details]

Abstract

VLSI technology at the micron and sub-micron level usually employs salicide technology. Here, titanium silicide is thermally reacted in a selective manner over the source, drain, and gate regions of an N or P channel FET. The thermal reaction includes annealing at 800oC. During this anneal, it has been observed that there is some loss of dopant from the silicon regions into the silicide and possibly some eventual evaporation of the dopant. This is shown in Fig. 1, where the loss of dopant (in this case boron) from single-crystal silicon, after the salicide process, is clearly seen. The consequence of this loss is as follows: The contact of the silicide to the silicon that is heavily doped is really a tunneling contact.