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Multiple Arithmetic Processors Within a Functional Co-Processor

IP.com Disclosure Number: IPCOM000039148D
Original Publication Date: 1987-Apr-01
Included in the Prior Art Database: 2005-Feb-01

Publishing Venue

IBM

Related People

Authors:
Danen, RJ Fabrizio, MF [+details]

Abstract

The use of a Restricted Instruction Set Computer (RISC) architecture, differing from the typical Von Neumann serial processing approach, allows simultaneous pipelining and processing of non-dependent data functions in a multiple processor (co-processor) environment. This approach is advanced by the use of multiple arithmetic execution units within one such co-processor. This co-processor is the Engineering Scientific Accelerator Floating Point Unit (ESA FPU) used in mid-range pipeline processors. This simultaneous execution is accomplished as described in the following. Illustrated in Fig. 1 is a simplified configuration of the mid- range pipeline processor.