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# Verifying the Operation of a Synchronous Binary Counter

IP.com Disclosure Number: IPCOM000039194D
Original Publication Date: 1987-May-01
Included in the Prior Art Database: 2005-Feb-01
Document File: 2 page(s) / 49K

IBM

## Related People

Fitchett, LW: AUTHOR

## Abstract

In a typical synchronous binary counter, polarity-hold latches hold the present count which is fed back to combinatorial increment logic, which in turn provides "count + 1" to the data input of the latches. When the primary increment control activates the primary clock line, the "count + 1" is loaded into the latches and the counter is updated. Referring to the figure, to validate operation of the counter, "parity predict" log is used. This logic predicts the parity for the next count value. When the primary clock line is activated and the count is updated, the parity bit is also updated. A parity checker at the output of the counter verifies that the predicted parity is correct for the count value. Thus, any single point of failure in the latches or the increment or the parity predict logic is detected.

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Verifying the Operation of a Synchronous Binary Counter

In a typical synchronous binary counter, polarity-hold latches hold the present count which is fed back to combinatorial increment logic, which in turn provides "count + 1" to the data input of the latches. When the primary increment control activates the primary clock line, the "count + 1" is loaded into the latches and the counter is updated. Referring to the figure, to validate operation of the counter, "parity predict" log is used. This logic predicts the parity for the next count value. When the primary clock line is activated and the count is updated, the parity bit is also updated. A parity checker at the output of the counter verifies that the predicted parity is correct for the count value. Thus, any single point of failure in the latches or the increment or the parity predict logic is detected. With continuing reference to Fig. 1, failures in the increment control logic or the clock line itself are detected by a "secondary increment control" while avoiding the redundancy of a duplicate secondary counter and related logic. The secondary increment control connects only to the low-order bit, which, for this example, is bit
7. Bit 7 toggles with every state change and, therefore, parity for the remaining bits must also toggle with every state change. Thus, bit 7 and the parity over bits 0-6 must track each other with every state change as shown in the table. Since bit 7 has its own clocking and control...